A variety of packaging approaches have been developed to address problems associated with packaging and interconnection of high pin count, high speed, high power digital semiconductor integrated devices. High pin counts, ranging from a few hundred input/output (I/O) pins to more than one thousand I/O pins, stress the capabilities of standard packages to efficiently connect the devices to a next level of interconnection (typically a printed circuit board (PCB)). One reference book which describes conventional packaging approaches, for example, is Tummala and Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York, 1988.
Perimeter lead devices require shrinking lead pitch and lead widths which create the limitations of: package sizes growing by the square of the I/O count, less tolerance in lead position and distortion, reduced placement tolerance in mounting the devices onto PCBs, and larger PCB area and costs.
Area array packages such as land grid arrays (LGAs) and ball grid arrays (BGAs) address several of the above described limitations of perimeter lead devices. LGA and BGA packages use an array of I/O sites to increase the number of I/O connections on a package while maintaining a larger pad pitch and a smaller package footprint. Typical pad pitches range from about 1.27 mm to about 1.5 mm. As the I/O connection count continues to increase, LGA and BGA packages increase in size and expense.
Chip Scale packaging (CSP) techniques can be used to reduce the device package to a size not much larger than the integrated circuit chip. Some of the techniques feature fine line pitch area array I/O pads to meet requirements of high pin count devices. Area array CSPs have pad pitches ranging from about 0.5 mm to about 1.0 mm, permitting four to ten times the I/O connection density as LGA or BGA packaged devices.
A flexible layer based CSP packaging approach using multi-chip module (MCM) techniques has been found to be highly efficient in packaging low to moderate I/O connection count devices and be capable of supporting 0.5 mm pitch arrays of pads within the footprint of a circuit chip or a footprint slightly larger than the chip. The process can alternatively be used to fan the I/O connections out to a larger pitch array to accommodate I/O limits of a PCB.
Although high I/O count CSP type packaged devices with tight pitches are area efficient and cost effective, the assembly of these devices on a PCB creates severe design constraints for an associated PCB. For example, a 400 I/O CSP with a 0.5 mm grid would include a solid array of 20 by 20 I/O pads in a tight footprint. The PCB needed to interconnect such a package would require expensive microvias (small blind holes between PCB interconnect layers) and fine pitch lines on a number (about 8-10) of layers with 75-100 .mu.m line widths and spaces and 50-75 .mu.m vias.
Furthermore, using CSP technologies can be expensive due to the fact that the package cost is primarily based on the processing area required by the package. Typically, in these embodiments, the chip is encapsulated. As the package footprint increases, warping and other stresses can occur in the encapsulation.
Thus, there is a particular need for a package and a fabrication method for high pin count devices which do not over-stress interconnect capabilities of a PCB.